Excitory and inhibitory cellular automata for computational networks

ABSTRACT

A set of three cellular automata-the E-Cell, the I-Cell, and the D-Node-can be used to design and assemble parallel processing networks for such applications as signal processing and artificial intelligence. The E-Cell (FIG. 1a) is an excitory cell. The I-Cell (FIG. 2a) is an inhibitory cell. The D-Node (FIG. 3) is a combination of E-Cells and I-Cells. The use of the cellular automata is illustrated in three exemplary applications: a lateral inhibition network (FIG. 5b), a tree-search network (FIG. 6b), and a graph-search network (FIG. 7e). In particular, the tree-search and graph-search networks are implemented using the same structure as the tree or graph.

This application is a Continuation of application Ser. No. 07/721,750,filed Jun. 26, 1991, now abandoned.

TECHNICAL FIELD OF THE INVENTION

The invention relates generally to computational networks, and moreparticularly relates to cellular automata for assembling computationalnetworks. In even greater particularity, three cellular automata--anexcitory E-Cell, an inhibitory I-Cell, and a delta D-Node (built from acombination of E- and I-Cells)--can be used to design and assembleparallel processing networks for such applications as signal processingand artificial intelligence.

BACKGROUND OF THE INVENTION

Cellular automata are computational logic cells that form the buildingblocks for cellular computational networks (or cellular automatom). Suchcellular networks are commonly used as the computational engines forimplementing parallel processing operations.

A cellular network is an interconnection of identical logic cells, wherea cell is a finite state machine. Each cell receives inputs from afinite set of neighbor cells, and possibly from an external source. Allcells compute one output simultaneously each clock cycle, with each cellproviding its output also to a set of neighbor cells, and possibly to anexternal receiver.

The specific problem to which the invention has application is thedesign of new cellular automata that can be assembled into cellularnetworks for parallel processing. These cellular automata should beuseful in the design and assembly of complex cellular networks for suchapplications as signal processing and artificial intelligence.

A large body of problems in signal processing and artificialintelligence can only be solved computationally by exploitingsignificant amounts of parallelism. The computational approach to theseproblems typically involves performing such tasks as graph searching andspatial filtering which are particularly amenable to parallelprocessing.

For a number of these applications, cellular automata have beenassembled into computer architectures for parallel processing. Recently,interest in computer architectures based on cellular automata hasincreased because of the significant potential for VLSI implementations.

However, initial attempts to use cellular automata assembled into linearsystems for parallel processing have failed to meet expectations, anduseful artificial intelligence problems remain for the most partcomputationally intractable. These systems have been found to be limitedby their structures in the degree of parallelism they can practicallyachieve.

One common application far parallel processing systems is to solveartificial intelligence problems involving graph searching. Graphsearching is required in a wide variety of artificial intelligenceapplications, including: Data base search, speech recognition (dynamictime warping), financial forecasting, operation management, trajectoryplanning, natural language interfaces, and learning systems.

Another typical application for parallel processing is two-dimensionalspatial filtering such as for image recognition applications.

Accordingly, a need exists for new cellular automata that can beassembled into cellular computational networks, such as for implementinggraph searching and spatial filtering in signal processing andartificial intelligence applications that use parallel processing.

SUMMARY OF THE INVENTION

The invention is a set of cellular automata for assembling computationalnetworks: (a) an excitory E-Cell, (b) an inhibitory I-cell, and (d) adelta D-Node built from a combination of E- and I-Cells. The cellularautomata can be used to design and assemble parallel processing networksfor such applications as signal processing and artificial intelligence.

In one aspect of the invention, the cellular automata include anexcitory E-Cell and an inhibitory I-Cell.

The E-Cell is characterized by a cell state vector V_(EC). It receives aplurality of inputs x_(n) with the values {-1, 0, +1}, and provides asingle output y₀ with the values {0, -1}. The output y₀ and the cellstate vector V_(EC) are determined in accordance with the followingrelationship: ##EQU1##

The inhibitory I-Cell is characterized by a cell state vector V_(IC). Itreceives a plurality of inputs x_(n) with the values {-1, 0, +1}, andprovides a single output y₀ with the values {0, +1}. The output y₀ andthe cell-state vector V_(IC) are determined in accordance with thefollowing relationship: ##EQU2##

In another aspect of the invention, the cellular automata includes adelta D-node that receives inputs x₀ and x₁, and provides an output y₀.The D-node is built from a single inhibitory I-Cell I₀, and threeexcitory E-Cells E₀, E₁, and E₂. The I-Cell I₀ is characterized by acell state vector voltage of V_(IC) =0. The E-Cells E₀ and E₁ arecharacterized by a cell state vector voltage of V_(EC) =0, and theE-Cell E₂ is characterized by a cell state vector voltage of V_(EC) >0.

The D-Node is configured such that (a) x₀ is applied to I₀, and to twoinputs of E₀, (b) x₁ is applied to I₀, and to two inputs of E₁, (c) E₀and E₁ also receive as inputs the output of I₀, (d) a fourth input toeach of E₀ and E₁ is the fed back output y₀, (e) the outputs of E₀ andE₁ provide the inputs to E₂, and (f) the output of E₂ provides theD-Node output y₀.

In an exemplary embodiment of the invention, the E-Cell and the I-Cellboth comprise summer logic, cell state vector logic and output logic.The summer logic sums the inputs x₀, x₁, . . . x_(n), and outputs anindication that the sum is either greater than, less than, or equal tozero. In response to the output of said summer logic, cell state vectorlogic respectively either increments, decrements, or does not modify thecell state vector. In response to the output of the cell state logic,output logic outputs (a) for the E-Cell a -1 and for the I-Cell a +1 ifthe cell state vector is less than zero, and (b) otherwise a zero.

The cellular automata can be used to assemble computational networks,such as a graph-search network that is isomorphic to the graphstructure, a tree-search network that is isomorphic to the treestructure, and a lateral inhibition network. An exemplary graph-searchnetwork uses D-nodes with the cell state vectors for the constituentE/I-Cells being selected to provide appropriate path weights, while anexemplary tree-search network uses E-Cells and I-Cells with the cellstate vectors being selected to provide appropriated branch weights.

The technical advantages of the invention include the following. The setof three cellular automata--excitory E-Cell, inhibitory I-Cell, anddelta D-node--can be used to assemble a wide variety of computationalnetworks, in particular graph-search and tree-search networks in whichthe networks are made isomorphic respectively to the graph and the treestructures. The E- and I-Cells can be assembled from standard logiccircuit building blocks, and the D-node can be assembled from E- andI-Cells.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the invention, and for furtherfeatures and advantages, reference is now made to the following DetailedDescription of an exemplary embodiment of the invention, taken inconjunction with the accompanying Drawings, in which:

FIGS. 1a and 1b respectively illustrate a generic excitory E-Cell and anexemplary E-Cell;

FIGS. 2a and 2b respectively illustrate a generic inhibitory I-Cell andan exemplary I-Cell;

FIG. 3 illustrates a delta D-Node assembled from one I-Cell and threeE-Cells;

FIG. 4 illustrates an exemplary circuit implementation of an E-Cell.

FIGS. 5a and 5b respectively illustrate an elementary combination of anE-Cell and an I-Cell, and a lateral-inhibition cellular network formedfrom E- and I-Cells;

FIGS. 6a and 6b respectively illustrate an exemplary tree structure andan exemplary E-Cell implementation of a corresponding cellulartree-search network;

FIGS. 6c, 6d, 6e, 6f, 6g and 6h illustrate an application of the E-Celltree-search network in computing a minimum cost path; and

FIGS. 7a, 7b, 7c, 7d, and 7e illustrate the design of an exemplarygraph-search network using D-Nodes.

DETAILED DESCRIPTION OF THE INVENTION

The Detailed Description of an exemplary embodiment of the cellularautomata--the E-Cell, the I-Cell, and the D-Node--as well as exemplarycellular network implementations of these cellular automatum, isorganized as follows:

1. Cellular Automata

1.1. The Excitory E-Cell

1.2. The Inhibitory I-Cell

1.3. The Delta D-Node

2. Cell Circuit Implementation

3. Exemplary Cellular Networks

3.1. Lateral-Inhibition Network

3.2. Tree-Search Network

3.3. Graph-Search Network

4. Parallel Processing Performance

5. Conclusion

The exemplary cellular automata are used in exemplarylateral-inhibition, tree-search, and graph-search networks for suchapplications as signal processing and strategy applications. However,the invention has general applicability to the design of cellularnetworks using one or more of the cellular automatum.

1. Cellular Automata. The cellular automata are of three types: (a) anexcitory or E-Cell; (b) an inhibitory or I-Cell; and (c) a delta orD-Node that is built from a combination of E- and I-Cells.

These cells can be used in the analysis, design, and assembly ofcellular computational networks. For example, by configuring suchcellular networks to have a similar structure to the graph or algorithmbeing examined, relatively complex computational networks can bedesigned and assembled.

This approach to cellular network design is adaptable to a wide varietyof applications, including parallel processing architectures for use insignal processing and artificial intelligence. For example, in the areaof signal processing, cellular networks can be designed to performspatial filtering for image processing applications (such as extractinginformation from an image for input to an artificial intelligence systemperforming image recognition). In the area of artificial intelligence,cellular networks can be designed to perform best-path analysis forrobotics systems.

1.1. The E-Cell. FIG. 1a functionally illustrates the excitory orE-Cell. The E-Cell receives inputs x₀, x₁, to x_(n), and produces asingle output y. The inputs may be provided by the cell's neighbors orfrom an external source.

The inputs to the E-Cell take on the values {-1, 0, 1}. The currentstate of the E-Cell is defined by the cell state vector V_(EC) whichtakes on the values { . . . , -1, 0, 1, . . . }. The output y takes onthe values {-1, 0}.

The output y and the cell state vector V_(EC) are determined accordingto the following algorithm: ##EQU3##

Referring to FIG. 1b, as an example of E-Cell operation, assume anE-Cell with one input x₀ and V_(EC) =3. When a series of excitatorysignals {-1, -1, . . . } are applied, the following time course results,where n is an interval and v(n) is the cell state vector for the currentstate:

    ______________________________________    n       xo(n)          v(n)   y(n)    ______________________________________    0       0              3      0    1       -1             2      0    2       -1             1      0    3       -1             0      0    4       -1             -1     -1    5       -1             -2     -1    ______________________________________

Thus, at time interval n=0 the cell state vector starts out at 3, andthe output is 0. After three excitory -1 inputs at time intervalsn=1,2,3, the cell state vector voltage is decremented to 0, and theoutput is still 0. At the next time interval n=4, an excitory -1 inputdecrements the cell state vector voltage to -1, and the output switchesto -1. Thus, the E-Cell acts like memory in that it can produce andstore different values.

1.2. The I-Cell. FIG. 2a functionally illustrates the inhibitory orI-Cell. The I-Cell receives inputs x₀, x₁, to x_(n), and produces asingle output y. The inputs may be provided by the cells neighbors orfrom an external source.

The inputs to the I-Cell take on the values {-1, 0, 1}. Associated withthe cell is a cell state vector V_(IC), taking on the values { . . . ,-1, 0, 1 . . . }. The output y takes on the values {0, 1}.

The determination of the output and updating of the cell state vectorV_(IC) are determined according to the following algorithm: ##EQU4##

Referring to FIG. 2b, as an example of E-Cell operation, assume anI-Cell with one input x₀ and V_(IC) =3. When a series of excitatorysignals {-1, -1, . . . } are applied, the following time course results,where n is an interval and v(n) is the cell state vector for the currentstate:

    ______________________________________    n       xo(n)          v(n)   y(n)    ______________________________________    0       0              3      0    1       -1             2      0    2       -1             1      0    3       -1             0      0    4       -1             -1     +1    5       -1             -2     +1    ______________________________________

Thus, at time interval n=0 the cell state vector starts out at 3, andthe output is 0. After three excitory -1 inputs at time intervalsn=1,2,3, the cell state vector voltage is decremented to 0, and theoutput is still 0. At the next time interval n=4, an excitory +1 inputdecrements the cell state vector voltage to +1, and the output switchesto +1. Thus, like the E-Cell, the I-Cell acts like memory in that it canproduce and store different values.

1.3. The D-Node. FIG. 3a functionally illustrates an exemplary delta orD-Node. The D-Node is built from a single inhibitory I-Cell I₀, andthree excitory E-Cells E₀, E₁, and E₂. The cell state vector voltage forI₀ is V_(IC) =0. The vector cell voltage for E₀ and E₁ is V_(EC) =0, andfor E₂ is V_(EC) >0.

The D-Node receives inputs x₀ and x₁, and provides a single output y₀.The input x₀ is applied to the inhibitory cell I₀, and to two inputs ofthe excitory cell E₀. The input x₁ is applied to the I₀, and to twoinputs of the excitory cell E₁. The excitory cells E₀ and E₁ alsoreceive as inputs the output of I₀. The fourth input to each of E₀ andE₁ is the fed back output of the D-Node y₀. The outputs of E₀ and E₁provide the inputs to excitory cell E₂, which provides the D-Node outputy₀.

To illustrate the function performed by this Node, suppose that asequence {-1, -1, . . . } is input at x₁. This input drives an I-CellI₀, which in turn increases the cell state vector voltage V_(EC) ofE-Cell E₀. It also drives E₁, which drives E₂, and thus decreases theV_(EC) of E₂.

The feedback from E₂ to E₀ cancels the effect of I₀ once the V_(EC) ofE₂ is equal to zero. Thus, the D-Node is capable of self regulation bytransferring state information from E₁ to E₀ or E₁, and regulating thistransfer.

2. Cell Circuit Implementation. The circuit implementation of theexemplary E-Cell and I-Cell, and therefore the D-Node, isstraightforward using standard TTL gates.

FIG. 4 illustrates an implementation for an E-Cell--the implementationfor the I-Cell is analogous, except that when the cell state vectorvoltage is less than one the output is inhibitory (+1) instead ofexcitory (-1).

Summer logic S sums the inputs x₀, x₁, . . . x_(n), and determines ifthe sum is either greater than, less than, or equal to zero.

Based on the output of the summer logic, cell state vector logic Vrespectively either increments, decrements, or does not modify the cellstate vector.

For the E-Cell, based on the output of the cell state logic, outputlogic Y outputs an excitory -1 if V<0, and otherwise outputs zero. Forthe I-Cell, the output logic outputs an inhibitory +1 if V<0, andotherwise outputs a zero.

Regarding driving the cell state voltage to a particular value, therecommended approach is to use an auxiliary network made up of similarcells--for example, a network that drives the primary network to aparticular state. An alternative approach, particularly suitable formulti-processors, is to have a host processor broadcast the appropriatecell state voltages to the processors that implement the cells.

The architecture of all of these cells could lend them to some novelsemiconductor implementations. The use of summation, threshold, andstate-vector (threshold) has similarities with the function of atransistor. Thus, these functions could be implemented using transistorsoperating in non-linear and linear ranges.

Some applications might best be served with slightly more elaboratecells. These could include an ALU, program counter, and a modestinstruction set. Making these units programmable would allow for a moregeneral purpose element. Other possible variations include implementingbinary logic and cells with state vectors taking on only two states.

3. Exemplary Cellular Networks. Cellular network design using theexemplary cellular automata can be used to analyze, design, and assemblea wide variety of cellular networks. Strictly by way of example, thedesign of cellular networks is described in connection with alateral-inhibition network, a tree-search network, and a graph searchnetwork.

These networks illustrate general cellular design considerations. Thedescription is given in the context of graph theory. Such an approach isadvantageous in that it provides a simple pictorial representation--suchan approach can be generalized to an approach based upon matrixrepresentations.

3.1. Lateral-Inhibition Network. FIGS. 5a and 5b illustrate anapplication of the cellular automata in implementing alateral-inhibition network using both excitory and inhibitory cells.

Referring to FIG. 5a, excitory and inhibitory cells E₀ and I₀ can becombined so that a single input signal will both excite and inhibit.Thus, an input excitory signal (-) produces an excitory output (-) fromE₀, and an inhibitory output (+) from I₀.

Referring to FIG. 5b, this principal can be used to assemble alateral-inhibition network. This network includes two inhibitory cellsI₀ and I₁, and five excitory cells E₀ -E₁. The cell state vector voltagefor both I₀ and I₁ is zero. The cell state vector voltages for E₀ -E₄and E₃ -E₄ are all greater than zero (inactive state), while the cellstate vector voltage for E₂ is less than zero (active state).

An excitory signal input (-) is applied (a) through I₀ to E₀ and E₁,through I₁ to E₃ and E₄, and (c) directly to E₂. The resulting networkoutputs from E₀ -E₁ and E₃ -E₄ are inhibited (+) while the output fromE₂ is excited (-).

The lateral-inhibition network can be used to integrate and sharpenspatial signals. For example, it has been proposed to perform imagefiltering and feature extraction as performed by the retina.

3.2. Tree-Search Network. FIGS. 6a-6h illustrate an application of thecellular automata in implementing a tree search algorithm using anetwork of E-Cells. In this example, the structure of the E-Cell networkis isomorphic to the tree structure.

Referring to FIGS. 6a and 6b, a tree structure is implemented using anequivalent E-Cell network. The single input to the tree is at the startnode S, and the four outputs of the tree search network are availablefrom the terminal nodes T₀ -T₃. The respective weights of the branchesof the tree are stored into the corresponding E-Cells as respective cellstate vector voltages.

A series of excitatory signals {-1, -1 . . . } drives the start node Sof the E-Cell network. In accordance with the E-Cell algorithm, when aterminal node T_(n) has a non-zero output, then the minimum cost pathhas been found.

Referring to FIGS. 6c-6h, the operation of the tree-search network isillustrated by the derivation of one solution to arriving at a minimumcost path in five clock cycles (unit time steps) n. Each FIGUREillustrates the state of the tree-search network at a respective one ofthe six clock cycles n=0-5.

A (+) is used to represent an inhibitory signal of +1, and a (-) is usedto represent an excitory signal of -1. In each FIGURE, the cell statevectors shown represent the current state. These states may be arrivedat in a number of ways, such as using the prior set-up proceduredescribed above.

At time n=5, a minimum cost path has been found, and is available atterminal node T₃.

3.3. Graph-Search Network. FIGS. 7a-7e illustrate an application of thecellular automata in implementing a graph-search algorithm usingD-Nodes. Again, the graph-search network is isomorphic to the graph ofinterest.

Referring to FIG. 7a, a single graphical element N₀ has two inputs x₀and x₁ and a single output y₀. The graphical element has a path weightof 5.

FIG. 7b illustrates an implementation of this graphical element usingtwo E-Cells EC₀ and EC₁ with respective inputs x₀ and x₁ and outputs y₀and y₁. Each E-Cell is set to the path weight of 5. However, for even amoderate sized graph, this E-Cell design could result in an explosion inthe number of cells necessary to implement a graph-search network.

FIG. 7c illustrates an alternative implementation of the graphicalelement using a single D-Node with respective inputs x₀ and x₁ andoutputs y₀ and y₁. The cell state vector of the D-Node is set to thepath weight 5.

Referring to FIGS. 7d-7e, the D-Node is used to implement a directedgraph constructed on a two-dimensional euclidean grid. FIG. 7dillustrates a graphical element N₀ implemented using two D-Nodes DN₀ andDN₁ with respective weights W₀ and W₁ --both of the inputs x₀ and x₁ areapplied to each D-Node which respectively provide the outputs y₀ and y₁.

FIG. 7e illustrates the D-Node implementation of a section of agraphical matrix. The matrix includes graphical elements N₀ -N₃ withfour inputs x₀ -x₃ and four outputs x₄ -x₇. The path weights are W₀ -W₃.The D-Node implementation uses four D-Nodes DN₀ -DN₃ with respectivecell state vectors corresponding to the path weights W₀ -W₁. The D-NodesDN₀ and DN₃ receive the inputs x₁ and x₂, while the D-Nodes DN₁ and DN₂receive respectively inputs x₃ and x₀ and respectively the outputs ofDN₀ and DN₃.

Thus, the effect of this approach to implementing a graph-search networkis that the network of cellular automata has the same structure as thegraph under analysis.

4. Parallel Processing Performance. The cellular automata can be used indesigning cellular computational networks that are able to exploitsignificant amounts of performance-enhancing parallelism.

As an example, consider the complexity of a max-flow algorithm. Themax-flow algorithm is the best approach currently available for findingthe minimum cost path through a directed graph from a start to aterminal vertex. On a serial machine it has a run time proportional to|V|³ where |V| is the number of vertices in the graph.

In contrast, for a graph-search cellular network implemented usingD-Nodes, the run time of a search is proportional to |V|. This assumesthat the graph-search network is designed to be isomorphic to the graphbeing searched.

As illustrated by the following table, in comparison with a serialmachine, a cellular network design is able to achieve a significantreduction in run time.

    ______________________________________                  Max-Flow  Cell-Net    |V|                  Run Time  Run Time    ______________________________________    1             1         1    2             8         2    8             512       8    512           1.3 × 10.sup.8                            512    ______________________________________

Thus, a direct correspondence exists between the size of the graph |V|and the cellular network implementation using D-Nodes, i.e., allowingthe graph to be implemented in hardware for optimum performance.

5. Conclusion. Although the Detailed Description of the invention hasbeen directed to certain exemplary embodiments, various modifications ofthese exemplary embodiments, as well as alternative embodiments, will besuggested to those skilled in the art. For example, the regularstructure of these elements makes it possible to implement graph-searcharrays of these cells much like memory cells. The cells would be madeaddressable, thus providing the user with the ability to configure graphweights so as to match a variety of graph structures. It would be usefulin some applications to integrate address or content addressable memoryonto the cells, placing the computer into the memory, and significantlyreducing the Von-Neumann bottleneck.

It is to be understood that the invention encompasses any modificationsor alternative embodiments that fall within the scope of the appendedclaims.

What is claimed:
 1. A graph-search network assembled from cellularautomata, comprising:a graph-search network configured fromappropriately intercoupled D-node cellular automata arranged to beisomorphic to a preselected graph structure; said D-node cellularautomata being configured from cellular automata that are an excitoryE-Cell and inhibitory I-Cell; said delta D-node receiving inputs, x₀ andx₁, and providing an output, y₀ ; said D-node being assembled from aninhibitory I-Cell, I₀, and three excitory E-Cells, E₀, E₁, and E₂ ; andsaid D-Node being configured such that (a) x₀ is applied to I₀ and totwo inputs of E₀, (b) x₁ is applied to I₀ and to two inputs of E₁, (c)E₀ and E₁ also receive as inputs the output of I₀, (d) a fourth input toeach of E₀ and E₁ is the fed back output y₀, (e) the outputs of E₀ andE₁ provide the inputs to E₂, and (f) the output of E₂ provides theD-Node output y₀ ; said E-Cell receives a plurality of inputs, x_(n),each with an input value of -1, 0, or +1 and provides a single output,y₀, with an output value of 0, or -1 that is determined in accordancewith the following state vector and input functional relationships:##EQU5## said I-Cell receives a plurality of inputs, x_(n), each with aninput value of -1, 0, or +1 and provides a single output, y₀, with anoutput value of 0, or +1 that is determined in accordance with thefollowing state vector and input functional relationships: ##EQU6##where V_(EC) and V_(IC) are cell state vectors.
 2. A computationalnetwork assembled from cellular automata, comprising:a computationalnetwork appropriately configured from intercoupled cellular automata, inwhich the cellular automata are cells, each having(i) a plurality ofinputs with each input having one of a plurality of preselected logicalvalues selected from the group consisting of -1, 0, and +1, (ii) asingle output having one of a plurality of preselected logical valuesselected from the group consisting of -1, 0, and +1 in response to avalue of a state vector, (iii) a state vector storage circuit forstoring said state vector having at least three distinct binary valuesincluding the group consisting of -1, 0, and +1, and (iv) circuitryconnected to said plurality of inputs and said state vector storagecircuit and operable such that the value of said state vector is(a)increased by a logical 1 if the sum of the input values is positive, (b)not changed if the sum of the input values is zero, (c) decreased by alogical 1 if the sum of the input values is negative.
 3. Thecomputational network of claim 2, wherein each of said cells comprise:anexcitory E-Cell or an inhibitory I-Cell; and wherein said single outputof said excitory E-Cell, y₀, has an output value of 0 or -1 that isgenerated in accordance with the following state vector and inputfunctional relationships:(i) if a summation of said plurality of inputsis 0, then said y₀ value is 0, (ii) if a summation of said plurality ofinputs is not 0, then said y₀ value is 0 if said state vector value is0, otherwise said y₀ value is -1; and wherein said single output of saidinhibitory I-Cell, y₀, has an output value of 0 or +1 that is generatedin accordance with the following state vector and input functionalrelationships:(i) if a summation of said plurality of inputs is 0, thensaid y₀ value is 0, (ii) if a summation of said plurality of inputs isnot 0, then said y₀ value is 0 if said state vector value is 0,otherwise said y₀ value is +1.
 4. The computational network of claim 3,wherein said cellular automata further comprises a delta D-node forreceiving inputs, x₀ and x₁, and providing an output, y₀ ;said D-nodebeing assembled from an inhibitory I-Cell, I₀, and three excitoryE-Cells, E₀, E₁, and E₂ ; and said D-node being configured such that (a)x₀ is applied to I₀ and to two inputs of E₀, (b) x₁ is applied to I₀ andto two inputs of E₁, (c) E₀ and E₁ also receive as inputs the output ofI₀, (d) a fourth input to each of E₀ and E₁ is the fed back output y₀,(e) the outputs of E₀ and E₁ provide the inputs to E₂, and (f) theoutput of E₂ provide the D-node output y₀.
 5. The computational networkof claim 3, wherein the computational network is a lateral-inhibitionnetwork comprising:inhibitory cells I₀ and I₁ and excitory cells E₀ -E₄; and said inhibitory and excitory cells being configured such that anexcitory signal input is applied(a) to I₀, I₁, and directly to E₂, (b)an output of I₀ is connected to E₀ and E₁, (c) an output of I₁ isconnected E₃ and E₄, such that the resulting network outputs from E₀ -E₁and E₃ -E₄ are inhibited while the resulting output from E₂ is excitedwhen the cell state vectors for both I₀ and I₁ is zero, the cell statevectors for E₀ -E₁ and E₃ -E₄ are all greater than zero, and the cellstate vector for E₂ is less than zero.
 6. The computational network ofclaim 2, wherein the computational network is a graph-search networkthat is isomorphic to a preselected graph structure.
 7. Thecomputational network of claim 2, wherein the computational network is atree-search network that is isomorphic to a preselected tree structure.8. Cellular automata for assembling computational networks,comprising:an inhibitory and excitory cell, each having(i) a pluralityof inputs with each input having one of a plurality of preselectedlogical values selected from the group consisting of -1, 0, and +1, (ii)a single output having one of a plurality of preselected logical valuesselected from the group consisting of -1, 0, and +1 in response to avalue of a state vector, (iii) a state vector storage circuit forstoring said state vector having at least three distinct binary valuesincluding the group consisting of -1, 0, and +1, and (iv) firstcircuitry connected to said plurality of inputs and said state vectorstorage circuit and operable such that the value of said state vectoris(a) increased by a logical 1 if the sum of the input values ispositive, (b) not changed if the sum of the input values is zero, (c)decreased by a logical 1 if the sum of the input values is negative. 9.The cellular automata of claim 8, wherein said excitory E-Cell, furthercomprises:said first circuitry connected to said plurality of inputsreceives inputs x₀, x₁, . . . x_(n), sums those inputs, and outputs anindication that the sum is either greater than, less than, or equal tozero; said state vector storage circuit comprises cell state logic forincrementing, decrementing, or not changing the cell state vector inresponse to said indication of said first circuitry; and output logicresponsive to the output of the cell state logic as follows:(i) if asummation of said plurality of inputs is 0, then said output value is 0,(ii) if a summation of said plurality of inputs is not 0, then saidoutput value is 0 if said state vector value is 0, otherwise said outputvalue is -1.
 10. The cellular automata of claim 8, wherein saidinhibitory I-Cell, further comprises:said first circuitry connected tosaid plurality of inputs receives inputs x₀, x₁, . . . x_(n), sums thoseinputs, and outputs an indication that the sum is either greater than,less than, or equal to zero; said state vector storage circuit comprisescell state logic for incrementing, decrementing, or not changing thecell state vector in response to said indication of said firstcircuitry; and output logic responsive to the output of the cell statelogic as follows:(i) if a summation of said plurality of inputs is 0,then said output value is 0, (ii) if a summation of said plurality ofinputs is not 0, then said output value is 0 if said state vector valueis 0, otherwise said output value is +1.
 11. The cellular automata ofclaim 8, wherein said single output of said excitory E-Cell, y₀, has anoutput value of 0 or -1 that is generated in accordance with thefollowing state vector and input functional relationships:(i) if asummation of said plurality of inputs is 0, then said y₀ value is 0,(ii) if a summation of said plurality of inputs is not 0, then said y₀value is 0 if said state vector value is 0, otherwise said y₀ value is-1; and wherein said single output of said inhibitory I-Cell, y₀, has anoutput value of 0 or +1 that is generated in accordance with thefollowing state vector and input functional relationships:(i) if asummation of said plurality of inputs is 0, then said y₀ value is 0,(ii) if a summation of said plurality of inputs is not 0, then said y₀value is 0 if said state vector value is 0, otherwise said y₀ value is+1.
 12. The cellular automata of claim 11, further comprising:a deltaD-node for receiving inputs, x₀ and x₁, and providing an output, y₀ ;and wherein said D-node is assembled from an I-Cell, I₀, and threeE-Cells, E₀, E₁, and E₂ ; and wherein said cells are configured suchthat(a) x₀ is applied to I₀ and to two inputs of E₀, (b) x₁ is appliedto I₀ and to two inputs of E₁, (c) E₀ and E₁ also receive as inputs theoutput of I₀, (d) a fourth input to each of E₀ and E₁ is the fed backoutput y₀, (e) the outputs of E₀ and E₁ provide the inputs to E₂, and(f) the output of E₂ provides the D-Node output y₀.
 13. A cellularautomata for assembling computational networks, comprising:a cell,having(i) a plurality of inputs with each input having one of aplurality of preselected logical values selected from the groupconsisting of -1, 0, and +1, (ii) a single output having one of aplurality of preselected logical values selected from the groupconsisting of -1, 0, and +1 in response to a value of a state vector,(iii) a state vector storage circuit for storing said state vectorhaving at least three distinct binary values, including the groupconsisting of -1, 0, and +1, and (vi) circuitry connected to saidplurality of inputs and said state vector storage circuit and operablesuch that the value of said state vector is(a) increased by a logical 1if the sum of the input values is positive, (b) not changed if the sumof the input values is zero, (c) decreased by a logical 1 if the sum ofthe input values is negative.
 14. The cellular automata of claim 13,wherein said cell is an excitory cell, and wherein said single output ofsaid excitory E-Cell, y₀, has an output value of 0 or -1 that isgenerated in accordance with the following state vector and inputfunctional relationships:(i) if a summation of said plurality of inputsis 0, then said y₀ value is 0, (ii) if a summation of said plurality ofinputs is not 0, then said y₀ value is 0 if said state vector value is0, otherwise said y₀ value is -1.
 15. The cellular automata of claim 13,wherein said cell is an inhibitory cell, and wherein said single output,y₀, has an output value of 0 or +1 that is determined in accordance withthe following state vector and input functional relationship:(i) if asummation of said plurality of inputs is 0, then said y₀ value is 0,(ii) if a summation of said plurality of inputs is not 0, then said y₀value is 0 if said state vector value is 0, otherwise said y₀ value is+1.
 16. A tree-search network assembled from cellular automata,comprising:cellular automata arranged and intercoupled to be isomorphicto a preselected tree structure; each cell having(i) a plurality ofinputs with each input having one of a plurality of preselected logicalvalues selected from the group consisting of -1, 0, and +1, (ii) asingle output having one of a plurality of preselected logical valuesselected from the group consisting of -1, 0, and +1 in response to avalue of a state vector, (iii) a state vector storage circuit forstoring said state vector having at least three distinct binary values,including the group consisting of -1, 0, and +1, and (iv) circuitconnected to said plurality of inputs and said state vector storagecircuit and operable such that the value of said state vector is(a)increased by a logical 1 if the sum of the input values is positive, (b)not changed if the sum of the input values is zero, (c) decreased by alogical 1 if the sum of the input values is negative.
 17. Thetree-search network of claim 16, wherein said cellular automata,comprise:an excitory E-Cell or an inhibitory I-Cell; and, wherein saidsingle output of said excitory E-Cell, y₀, has an output value of 0 or-1 that is generated in accordance with the following state vector andinput functional relationships:(i) if a summation of said plurality ofinputs is 0, then said y₀ value is 0, (ii) if a summation of saidplurality of inputs is not 0, then said y₀ value is 0 if said statevector value is 0, otherwise said y₀ value is -1; and wherein saidsingle output of said inhibitory I-Cell, y₀, has an output value of 0 or+1 that is generated in accordance with the following state vector andinput functional relationships:(i) if a summation of said plurality ofinputs is 0, then said y₀ value is 0, (ii) if a summation of saidplurality, of inputs is not 0, then said y₀ value is 0 if said statevector value is 0, otherwise said y₀ value is +1.